2006 08 01

A simple 4-letter word defines a revolution at Intel.


While Moore's Law remains unbroken, the factor of power becomes ugly.  Without fundamental re-architecture, subsequent increases in performance require exponential increases in power (energy).  Ironically, as we become ever more mindful of the tradeoff between performance and energy as in cars and homes, Intel has wrestled with the same trade-off extending Moore's Law.  Gordon Moore, Intel founder, accurately predicted, in 1965, that the number of transistors on a chip doubles about every two years.   http://www.intel.com/technology/silicon/mooreslaw/index.htm:

There is a linear relation between transistor count and processor performance.  For a given transistor count, the equation includes the factor Instructions Per Second:

Performance = Frequency * IPS

The user wants maximum performance but is increasingly irritated, especially if mobile, by the undesirable byproducts of power requirements:  decreased battery time, heat, and fan noise.  The need for processor Power, generally half of the computing requirement, is based on:

Power = Frequency * Voltage * Capacitance

Thus, while User desires drive up frequency and transistor count, intel has decreased voltage and capacitance requirements by decreasing conductor width.  The new processors, named simply "core" feature 65nm copper conductors linking over 1 billion transistors.  But to further minimize power intel has begun to turn back the trend toward higher frequency.  The new quest is to accomplish more with each instruction and with each clock cycle, so frequency can decline.  Once the core processor is optimally efficient, two cores may be produced on the same chip to cooperatively process twice the instructions.  The number of cores per chip may now well double every two years keeping Moore's Law intact.

On each multi-core chip, common access to increasing volumes of level 2 cache further extend performance headroom.

The arrangement of transistors on the chip is guided by micro-architecture.  Intel's leading micro-architect of the Intel Architecture (IA) core processor is Ofri Wechsler.  His presentation details the 5 aspects of improvement leading to revolutionary headroom going forward in PPW:

  1. wide dynamic execution
  2. intelligent power capability
  3. advanced smart cache
  4. smart memory access
  5. advanced digital media boost

Just as we speak of "miles per gallon", for processors the new language is performance per watt.